In marketing a family of data processing systems, it is common practice to offer systems with different processing speed capabilities which include central processing units (CPUs) that are essentially the same except for the processing speed rating. It is therefore necessary to provide modifications to the circuitry governing the rate of instruction execution for slowing down the processing speeds of the derated CPUs.
Such modifications may be as simple as providing a slower system clock, but this technique may present problems because of potentially troublesome effects on system components other than the CPU(s). This approach can also cause subtle timing problems in the CPU(s) themselves, particularly in the case of pipelined CPUs such as those typically used in powerful mainframe computer systems.
Thus, those skilled in the art will understand that it would be desirable to effect submodel control in such a manner that reliable system operation is absolutely unaffected and the rate of operation is established at a precise fraction of full speed for the execution of each instruction, even for instructions whose period of execution may be variable.